1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly, to a circuit configuration capable of varying a voltage level for precharging a bit line.
2. Description of the Background Art
In a wafer testing process in course of manufacturing a semiconductor device such as a dynamic random access memory (DRAM), wafer testing is generally conducted before tuning an internal voltage, by externally applying a voltage for precharging a bit line.
In the DRAM and others, however, there are cases where a word line and a bit line have been short-circuited with each other in the wafer testing process.
An example of such a case is shown in FIG. 12, which is a circuit diagram of a portion including a memory cell MC1 in a memory cell array of the DRAM, in which a word line WL2 and a bit line BL2 are short-circuited.
Referring to FIG. 12, memory cell MC1 includes a transistor NN1 and a capacitor CC1.
To access memory cell MC1, word line WL1 is activated to an H level, while word line WL2 is maintained at a non-accessed state of an L level.
In this state, if bit line BL1 and word line WL2 are short-circuited, the voltage for precharging the bit line, which is originally set half a value of an internal power supply voltage VCCS, i.e., xc2xd (VCCS), would be affected by the L level of word line WL2, so that it would become a value lower than the desired voltage level.
At the time of reading out xe2x80x9cLxe2x80x9d data of memory cell MC1, if the precharge voltage of the bit line is made lower than the original value due to the short circuit, as shown in FIG. 13, the reading of the xe2x80x9cLxe2x80x9d data becomes difficult, and there is a high possibility that the read data of the xe2x80x9cLxe2x80x9d level from memory cell MC1 may be misread as an xe2x80x9cHxe2x80x9d level.
At the time of wafer testing, however, the precharge voltage of the bit line is externally supplied. Thus, even if such a short circuit takes place, the value of the precharge voltage of the bit line is stable in the normal operation, making it impossible to find the abnormality.
Therefore, defects due to such abnormality of the precharge voltage of the bit line cannot be rejected or relieved, causing degradation of the yield.
An object of the present invention is to provide a circuit that is capable of varying a bit line voltage to accelerate a defect of a bit line, so that the bit line defect due to an abnormal bit line voltage can be rejected and relieved.
The semiconductor integrated circuit according to an aspect of the present invention includes: a memory cell array region having a plurality of memory cells arranged in rows and columns, a plurality of word lines provided corresponding to the rows of the memory cells, and a plurality of bit lines provided corresponding to the columns of the memory cells; and a voltage generating circuit receiving a first power supply voltage for generating a bit line voltage for use in precharging said plurality of bit lines. The voltage generating circuit includes: a voltage transforming circuit receiving the first power supply voltage to generate a second power supply voltage having a voltage level equivalent to a reference value of the bit line voltage; and a voltage control circuit receiving the second power supply voltage for outputting the bit line voltage. The voltage control circuit includes at least one of a voltage boost circuit boosting the second power supply voltage supplied to generate the bit line voltage, and a voltage step-down circuit reducing the second power supply voltage supplied to generate the bit line voltage.
Preferably, the voltage control circuit includes both the voltage boost circuit and the voltage step-down circuit. The voltage control circuit further includes a judging circuit selectively supplying the second power supply voltage to either one of the voltage boost circuit and the voltage step-down circuit in a test mode, according to an external command.
Preferably, the voltage control circuit further includes a voltage transmitting unit, provided between the voltage transforming circuit and the plurality of bit lines and the voltage control circuit outputs the second power supply voltage by use of the voltage transmitting unit as the bit line voltage in a mode other than the test mode.
According to the semiconductor integrated circuit described above, it becomes possible to detect a defect of the bit line caused by an abnormal bit line voltage.
Preferably, the voltage control circuit includes the voltage boost circuit, the voltage step-down circuit, and a voltage transmitting unit for supplying the second power supply voltage as the bit line voltage. The voltage control circuit further includes a judging circuit for selectively supplying the second power supply voltage to one of the voltage boost circuit, the voltage step-down circuit and the voltage transmitting unit, according to a comparison between the bit line voltage and a reference voltage.
According to the semiconductor integrated circuit described above, it becomes possible to relieve the defect of the bit line due to the abnormal bit line voltage, and thus to improve the yield.
Preferably, the voltage generating circuit includes: a plurality of first resistance elements connected in series between a first power supply node supplying the first power supply voltage and a first internal node; a plurality of second resistance elements connected in series between a second power supply node supplying a third power supply voltage and the first internal node; a first switch circuit for short-circuiting at least one of the plurality of first resistance elements; according to an external command and a second switch circuit for short-circuiting at least one of the plurality of second resistance elements according to an external command.
In particular, the first and second switch circuits include a plurality of transistors connected in parallel with the first and second resistance elements, respectively. In the test mode, at least one of the plurality of transistors is turned on according to a test signal.
According to the semiconductor integrated circuit described above, it becomes possible to detect a defect of the bit line caused by an abnormal bit line voltage.
In particular, the first and second switch circuits include a plurality of fuses that can be externally burnt in a non-volatile manner, which are connected in parallel with the first and second resistance elements, respectively.
According to the semiconductor integrated circuit described above, it becomes possible to relieve the defect of the bit line due to the abnormal bit line voltage, and thus to improve the yield.
The semiconductor integrated circuit according to another aspect of the present invention includes: a memory cell array region having a plurality of memory cells arranged in rows and columns, a plurality of word lines provided corresponding to the rows of the memory cells and a plurality of bit lines provided corresponding to the columns of the memory cells; and a voltage generating circuit receiving a plurality of first power supply voltages for generating a bit line voltage for precharging the plurality of bit lines. The voltage generating circuit includes: the voltage control circuit selecting one of supplied plurality of first power supply voltage to output as an internal voltage in a test mode, according to an external command; and a voltage transforming circuit receiving the internal voltage to generate the bit line voltage.
Preferably, the voltage transforming circuit includes: a plurality of first resistance elements connected in series between a first internal node supplied with the internal voltage and a second internal node to supply the bit line voltage; a plurality of second resistance elements connected in series between a second power supply node supplying a second power supply voltage and the second internal node; a first switch circuit for short-circuiting at least one of the plurality of first resistance elements according to an external command; and a second switch circuit for short-circuiting at least one of the plurality of second resistance elements according to an external command.
In particular, the first and second switch circuits include a plurality of transistors connected in parallel with the first and second resistance elements, respectively. In the test mode, at least one of the plurality of transistors is turned on according to a test signal in each of the first and second switch circuit.
According to the semiconductor integrated circuit described above, it becomes possible to detect a defect of the bit line caused by an abnormal bit line voltage.
In particular, the first and second switch circuits include a plurality of fuses that can be externally burnt in a non-volatile manner, which are connected in parallel with the first and second resistance elements, respectively.
According to the semiconductor integrated circuit described above, it becomes possible to relieve the defect of the bit line due to the abnormal bit line voltage, and thus to improve the yield.
The semiconductor integrated circuit according to yet another aspect of the present invention includes: a memory cell array region having a plurality of memory cells arranged in rows and columns, a plurality of word lines provided corresponding to the rows of the memory cells and a plurality of bit lines provided corresponding to the columns of the memory cells; and a voltage generating circuit receiving a first power supply voltage for generating a bit line voltage in an internal node for use in precharging the plurality of bit lines. The voltage generating circuit includes: a plurality of first resistance elements connected in series between a first power supply node supplying the first power supply voltage and a first internal node; a plurality of second resistance elements connected in series between a second power supply node supplying a second power supply voltage and the internal node; a first switch circuit for short-circuiting at least one of the plurality of first resistance elements according to external a command; and a second switch circuit for short-circuiting at least one of the plurality of second resistance elements.
Preferably, the first and second switch circuits include a plurality of transistors connected in parallel with the first and second resistance elements, respectively. In the test mode, at least one of the plurality of transistors is turned on according to a test signal.
According to the semiconductor integrated circuit described above, it becomes possible to detect a defect of the bit line caused by an abnormal bit line voltage.
Preferably, the first and second switch circuits include a plurality of fuses that can be externally burnt in a non-volatile manner, which are connected in parallel with the first and second resistance elements, respectively.
According to the semiconductor integrated circuit described above, it becomes possible to relieve the defect of the bit line due to the abnormal bit line voltage, and thus to improve the yield.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.